Embodiments of the invention relate generally to structures and methods for packaging semiconductor devices and, more particularly, to a surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections.
Surface-mount technology is a method for constructing electronic circuits in which surface mount components or packages are mounted directly onto the surface of printed circuit boards (PCBs) or other similar external circuits. In the industry, surface-mount technology has replaced the through-hole technology construction method of fitting components with wire leads into holes in the circuit board.
One common type of component that is surface-mounted is a power semiconductor device, which is a semiconductor device used as a switch or rectifier in power electronic circuits, such as switched mode power supplies, for example. Most power semiconductor devices are only used in commutation mode (i.e., they are either on or off), and are therefore optimized for this. Many power semiconductor devices are used in high voltage power applications and are designed to carry a large amount of current and support a large voltage. In use, high voltage power semiconductor devices are surface mounted to an external circuit by way of a power overlay (POL) packaging and interconnect system, with the POL package also providing a way to remove the heat generated by the device and protect the device from the external environment.
A standard POL package manufacturing process typically begins with placement of one or more power semiconductor devices onto a dielectric layer by way of an adhesive. Metal interconnects (e.g., copper interconnects) are then electroplated onto the dielectric layer to form a direct metallic connection to the power semiconductor device(s), so as to form a POL sub-module. The metal interconnects may be in the form of a low profile (e.g., less than 200 micrometers thick), planar interconnect structure that provides for formation of an input/output (I/O) system to and from the power semiconductor device(s). The POL sub-module is then soldered to a ceramic substrate (Alumina with DBC, AlN with AMB Cu, etc.) using soldered interconnection for electrical and thermal connectivity. The gaps around the semiconductor between the POL dielectric layer and the ceramic substrate are then filled using a dielectric organic material using either capillary flow (capillary underfill), no-flow underfill or injection molding (molding compounds) to form the POL package.
In existing surface-mounted POL packages, the long term reliability of the package is limited by thermo-mechanical stresses that are generated due to the varying thermal expansion coefficients (CTEs) of the constituent materials. More specifically, the varying CTEs of the dielectric organic material/underfill and ceramic substrate of the POL package leads to thermal and bending stresses in the underfill and ceramic substrate. These thermal and bending stresses in the underfill and ceramic substrate can in turn lead to warping of the package. When warping of the package occurs, the reliability of second-level interconnections of the package is affected.
Therefore, it would be desirable to provide a surface-mount package having a stress balance-based design strategy that reduces package warpage and thermal stress, such that the package reliability in thermal cycling can be improved. It would further be desirable for such a package design strategy to improve the reliability of the second-level interconnections.